VLSI Implementation of a 2x2 MIMO-OFDM System on FPGA

-Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) technology is an attractive transmission technique for wireless communication systems with multiple antennas at transmitter and receiver. The core of this technology is that it divides one data stream to many. Hence, data rate, reliability and diversity can be increased along with the stability for multipath signals. FPGA implementation is carried with good channel estimation method, efficient FFT/IFFT processor and better coding techniques. This work describes the efficient implementation of a Low-Power 64-point Pipeline FFT/IFFT processor adopting a single-path delay feedback style. The proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming less power. Headerbased channel estimation with maximum likelihood algorithm is chosen in consideration of hardware feature as well as communication theory for fast prototyping. The pipeline architecture here includes the simple logic of one adder and channel memories without redundancy. Thus reducing the complexity from O (n 2 ) to O (1), it saves 43 percent of the hardware resources and achieves a better performance in the architecture. Keywords--MIMO-OFDM, FFT/IFFT, Channel Estimation, FPGA